In integrated circuits there is often the need to have a number of different operating voltages. MOS devices are typically operated at nominal voltages Vdd. In some instances, such as power management circuits, the circuits might need to be operated at voltages in excess of Vdd of the circuits. In these cases, high-voltage drain metal-oxide-semiconductor (HVD-MOS) devices capable of operating at high voltages on the drain side are required.
FIG. 1 illustrates a conventional HVD-MOS device, which includes a source region 4, a drain region 6 and a very lightly-doped drain extension region 8. Drain extension region 8 preferably extends under gate 10. Typically, drain extension region 8 has an impurity concentration several orders lower than typical lightly-doped source/drain (LDD) regions. The depth of the drain extension region 8 is also greater. Source region 4, drain region 6 and drain extension region 8 are formed in substrate 2. A well region 14, which has a different conductivity type than source and drain regions 4 and 6, may be formed adjacent to drain extension region 8 and extending toward the source side.
HVD-MOS devices may be used in applications where the voltage on the drain exceeds the normal voltage rating of the gate oxide. HVD-MOS devices differ from regular self-aligned MOS devices in that they use a very lightly-doped extension region, which depletes at high drain voltages. This allows much of voltage to be dropped across the extension region, and thus reduces the electric field across the gate oxide to a safe level. HVD-MOS devices are suitable for power amplifiers and power conditioning circuits, and are generally more robust than conventional MOS devices having the same thickness of gate dielectric. In particular, it is not necessary to add extra drain implants to control channel hot carrier (CHC) effects, and the higher breakdown voltage simplifies circuit design if HVD-MOS devices are used for electrostatic discharge (ESD) protection. For example, with HVD-MOS devices being used, it is normally unnecessary to include resistors in series with application specific integrated circuit (ASIC) outputs.
Typically, to incorporate HVD-MOS devices into a CMOS integrated circuit, additional and special processes are required. These processes add cost and complexity to the manufacturing process of the integrated circuit. Further processes with lower cost and less complexity are thus needed.